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features ? pwm and direction-controlled driving of fo ur externally-powered nmos transistors ? high temperature capabili ty up to 200c junction ? a programmable dead time is included to avoid peak currents within the h-bridge ? integrated charge pump to provide gate vo ltages for high-side drivers and to supply the gate of the ex ternal battery reverse protection nmos ? 5v/3.3v regulator and current limitation function ? reset derived from 5v/3.3v regulator output voltage ? a programmable window watchdog ? battery overvoltage protection and battery undervoltage management ? overtemperature warning and protection (shutdown) ? high voltage serial inte rface for communication ? qfn32/tpqfp package 1. description the ata6824 is designed for dc motor control application in automotive high temper- ature environment like in mechatronic assemblies in the vicinity of the hot engine, e.g. turbo charger. with a maximum junction temperature of 200c, ata6824 is suitable for applications with an ambient temperature up to 150c. the ic includes 4 driver stages to control 4 external power mosfets. an external microcontroller provides the direction signal and the pwm frequency. in pwm opera- tion, the high-side switches are permanently on while the low-side switches are activated by the pwm frequency. ata6824 contains a voltage regulator to supply the microcontroller; via the input pin vmode the output voltage can be set to 5v or 3.3v respectively. the on-chip window watchdog timer provides a pin-programmable time window. the watchdog is internally trimmed to an accuracy of 10%. for communication a high volt- age serial interface with a maximum data range of 20 kbaud is integrated. high temperature h-bridge motor driver ata6824 4931k?auto?06/10
2 4931k?auto?06/10 ata6824 figure 1-1. block diagram vmode /reset microcontroller logic control vcc tp2 wd 12v regulator vint 5v regulator otp 12 bit oscillator vcc 5v regulator bandgap charge pump hs driver 2 vres h2 cp cp cplo vbatsw vbat vbat battery vbg pbat vint vg cpih h1 m s1 s2 l2 vbat gnd dg3 tp1 sio cc dg2 pgnd l1 ot uv ov hs driver 1 r gate r gate r gate r gate ls driver 2 supervisor cc timer wd timer serial interface ls driver 1 dir tx rx pwm dg1 c vres c cp c vg c vint c vcc c cc r cc r rwd c sio
3 4931k?auto?06/10 ata6824 2. pin configuration figure 2-1. pinning qfn32/tpqfp32 note: yww date code (y = year - above 2000, ww = week number) ata6824 product name zzzzz wafer lot number al assembly sub-lot number vmode vint rwd cc /reset wd gnd sio vg cplo cphi vres h2 s2 h1 s1 tp2 vbatsw vbat vcc pgnd l1 l2 pbat tx dir pwm tp1 rx dg3 dg2 dg1 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 atmel yww ata6824 zzzzz-al table 2-1. pin description pin symbol i/o function 1 vmode i selector for v cc and interface logic voltage level 2 vint i/o blocking capacitor 220 nf/10v/x7r 3 rwd i resistor defining the watchdog interval 4 cc i/o rc combination to adjust cross conduction time 5 /reset o reset signal for microcontroller 6 wd i watchdog trigger signal 7 gnd i ground for chip core 8 sio i/o high voltage (hv) serial interface 9 tx i transmit signal to serial interface from microcontroller 10 dir i defines the rotation direction for the motor 11 pwm i pwm input controls motor speed 12 tp1 ? test pin to be connected to gnd 13 rx o receive signal from serial interface for microcontroller 14 dg3 o diagnostic output 3 15 dg2 o diagnostic output 2 16 dg1 o diagnostic output 1 17 s1 i/o source voltage h-bridge, high-side 1 18 h1 o gate voltage h-bridge, high-side 1 19 s2 i/o source voltage h-bridge, high-side 2 20 h2 o gate voltage h-bridge, high-side 2 21 vres i/o gate voltage for reverse protecti on nmos, blocking capacitor 470 nf/25v/x7r
4 4931k?auto?06/10 ata6824 3. general statement and conventions ? parameter values given without tolerances are indicative only and not to be tested in production ? parameters given with tolerances but without a parameter number in the first column of parameter table are ?guaranteed by design? (mainly covered by measurement of other specified parameters). these parameters are not to be tested in production. the tolerances are given if the knowledge of the parameter tolerances is important for the application ? the lowest power supply voltage is named gnd ? all voltage specifications are referred to gnd if not otherwise stated ? sinking current means that the current is flowing into the pin (value is positive) ? sourcing current means that the current is flowing out of the pin (value is negative) 3.1 related documents ? qualification of integrated circuits according to atmel ? hno procedure based on aec-q100 ? aec-q100-004 and jesd78 (latch-up) ? esd stm 5.1-1998 ? cei 801-2 (only for information regarding esd requirements of the pcb) 22 cphi i charge pump capacitor 220 nf/25v/x7r 23 cplo o 24 vg i/o blocking capacitor 470 nf/25v/x7r 25 pbat i power supply (after reverse prot ection) for charge pump and h-bridge 26 l2 o gate voltage h-bridge, low-side 2 27 l1 o gate voltage h-bridge, low-side 1 28 pgnd i power ground for h-bridge and charge pump 29 vcc o 5v/100 ma supply for microcontroller, blocking capacitor 2.2 f/10v/x7r 30 vbat i supply voltage for ic core (after reverse protection) 31 vbatsw o 100 pmos switch from v bat 32 tp2 ? test pin to be connected to gnd table 2-1. pin description (continued) pin symbol i/o function
5 4931k?auto?06/10 ata6824 4. application 4.1 general remark this chapter describes the principal application for which the ata6824 was designed. because atmel cannot be considered to understand fully all aspects of the system, application and envi- ronment, no warranties of fitness for a particular purpose are given. 5. functional description 5.1 power supply unit wi th supervisor functions 5.1.1 power supply the ic is supplied by a reverse-protected battery voltage. to prevent it from destruction, proper external protection circuitry has to be added. it is recommended to use at least a capacitor com- bination of storage and hf caps behind the reverse protection circuitry and closed to the vbat pin of the ic (see figure 1-1 on page 2 ). an internal low-power and low drop regulator (v int ), stabilized by an exte rnal blocking capacitor, provides the necessary low-voltage supply for all internal blocks except the digital io pins. this voltage is also needed in the wake-up process. the low-power band gap reference is trimmed and is used for the bigger vcc regulator, too. all internal blocks are supplied by the internal regulator. note: the internal supply voltage v int must not be used for any other supply purpose! nothing inside the ic except the logic interface to the microcontroller is supplied by the 5v/3.3v vcc regulator. a power-good comparator checks the output voltage of the v int regulator and keeps the whole chip in reset as long as the voltage is too low. there is a high-voltage switch which brings out the battery voltage to the pin vbatsw for mea- surement purposes. this switch is switched on for vcc = high and stays on in case of a watchdog reset. the signal can be used to switch on external voltage regulators, etc. table 4-1. typical external components (see also figure 1-1 on page 2 ) component function value tolerance c vint blocking capacitor at vint 220 nf, 10v, x7r 50% c vcc blocking capacitor at vcc 2.2 f, 10v, x7r 50% c cc cross conduction time definition capacitor typical 680 pf, 100v, cog r cc cross conduction time definition resistor typical 10 k c vg blocking capacitor at vg typical 470 nf, 25v, x7r 50% c cp charge pump capacitor typical 220 nf, 25v, x7r c vres reservoir capacitor typical 470 nf, 25v, x7r r rwd watchdog time definition resistor typical 51 k c sio filter capacitor for sio typical 220 pf, 100v
6 4931k?auto?06/10 ata6824 5.1.2 voltage supervisor this block is intended to protect the ic and the external power mos transistors against overvolt- age on battery level and to manage undervoltage on it. function: in case of both overvoltage alarm (v thov ) and of undervoltage alarm (v thuv ) the exter- nal nmos motor bridge tr ansistors will be switched off. the failure state will be flagged via dg2. no other actions will be carried ou t. the voltage superv ision block is connec ted to vbat and fil- tered by a first-order low pass with a corner frequency of typical 15 khz. 5.1.3 temperature supervisor there is a temperature sensor integrated on-chip to prevent the ic from overheating due to a failure in the external circuitry and to protect the external nmosfet transistors. in case of detected overtemperature (180c), the diagnostic pin dg3 will be switched to ? h? to signalize overtemperature warning to the microc ontroller. it should undertake actions to reduce the power dissipation in the ic. in case of detected overtemperature (200c), the v cc regulator and all drivers including the serial interface will be switched off immediately and /reset will go low. both temperature thresholds are correlated. the absolute tolerance is 15k and there is a built-in hysteresis of about 10k to avoid fast oscillations. after cooling down below the 170c threshold; the ic will go into active mode. the occurrence of overtemperature shutdown is latched in dg3. dg3 stays on high until first wd trigger. 5.2 5v/3.3v vcc regulator the 5v/3.3v regulator is fully integrated on-chip. it requires only a 2.2 f ceramic capacitor for stability and has 100 ma current capability. using the vmode pi n, the output voltage can be selected to either 5v or 3.3v. switching of the output voltage during operation is not intended to be supported. the vmode pin must be hard-wired to either vint for 5v or to gnd for 3.3v. the logic high level of the microc ontroller interface will be adapted to the vcc regulator voltage. the output voltage accuracy is in general < 3%; in the 5v mode with v vbat < 9v it is limited to <5%. to prevent destruction of the ic, the current delivered by the regulator is limited to maximum 100 ma to 350 ma. the delivered voltag e will break down and a reset may occur. please note that this regulator is the main heat source on the chip. the maximum output current at maximum battery voltage and high ambient temperature can only guaranteed if the ic is mounted on an efficient heat sink. a power-good comparator checks the output voltage of the vcc regulator and keeps the exter- nal microcontroller in reset as long as the voltage is too low.
7 4931k?auto?06/10 ata6824 figure 5-1. voltage dependence and timing of vcc controlled reset figure 5-2. correlation between vcc output voltage and reset threshold the voltage difference between the regulator output voltage and the upper reset threshold volt- age is bigger than 75 mv (vmode = high) and bigger than 50 mv (vmode = low). 5.3 reset and watchdog management the timing basis of the watchdog is provided by the trimmed internal osc illator. its period t osc is adjustable via the external resistor r wd . the watchdog expects a triggering signal (a rising edge) from the microcontroller at the wd input within a period time window of t wd . figure 5-3. timing diagram of the watchdog function t res t delayresl vcc 5v v thres / reset v cc1-vthresh = v cc1 - v thresh 5.15v 4.9v 4.85v 4.1v v cc1 v thresh tracking voltage v cc1-thresh vcc t 2 t 1 t 2 t 1 t d t d t resshort t res wd /reset
8 4931k?auto?06/10 ata6824 5.3.1 timing sequence for example, with an external resistor r wd =33k 1% we get the follo wing typical parameters of the watchdog. t osc = 12.32 s, t 1 = 12.1 ms, t 2 = 9.61 ms, t wd = 16.88 ms 10% the times t res = 70 ms and t d = 70 ms are fixed values with a tolerance of 10%. after ramp-up of the battery voltage (power-on reset), the v cc regulator is sw itched on. the reset output, /reset, stays low for the time t res , then switches to high. for an initial lead time t d (for setups in the controller) the watchdog waits for a rising edge on wd to start its normal win- dow watchdog sequence. if no rising edge is detected, th e watchdog will reset the microcontroller for t res and wait t d for the rising edge on wd. times t 1 (close window) and t 2 (open window) form the window watchdog sequence. to avoid receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the timeframe of t 2 = 9.61 ms. the trigger event will re start the watchdog sequence. figure 5-4. t wd versus r wd if triggering fails, /reset will be pulled to ground for a shortened reset time of typically 2 ms. the watchdog start sequence is similar to the power-on reset. the internal oscillator is trimmed to a tolerance of < 10%. this means that t 1 and t 2 can also vary by 10%. the following calculation show s the worst case calculation of the watchdog period t wd which the microcontroller has to provide. t 1min = 0.90 t 1 = 10.87 ms, t 1max = 1.10 t 1 = 13.28 ms t 2min = 0.90 t 2 = 8.65ms, t 2max = 1.10 t 2 = 10.57 ms t wdmax = t 1min + t 2min = 10.87 ms + 8.65 ms = 19.52 ms t wdmin = t 1max = 13.28 ms t wd = 16.42 ms 3.15 ms (19.1%) figure 5-4 on page 8 shows the typical watchdog period t wd depending on the value of the external resistor r osc . a reset will be active for v cc < v thresx ; the level v thresx is realized with a hysteresis (hys resth ). rwd (k ) twd (ms) max min 0 10 20 30 40 50 60 10 20 30 40 50 60 70 80 90 100 typ
9 4931k?auto?06/10 ata6824 5.4 high voltage serial interface a bi-directional bus interface is implemented for data transfer between hostcontroller and the local microcontroller (sio). the transceiver consists of a low side driver (1.2v at 40 ma) with slew rate control, wave shap- ing, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver. 5.4.1 transmit mode during transmission, the da ta at the pin tx will be transferred to the bus driver to generate a bus signal on pin sio. the pin tx has a pull-down resistor included. to minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave-shaping un it. in transmit mode, transmission will be in terrupted in case of overheating at the sio driver. 5.4.2 reset mode in case of an active reset show n at pin /reset the pin sio is switched to low, independent of the temperature. the maximum current is limited to i sio_lim_reset . figure 5-5. definition of bus timing parameters the recessive bus level is generated from the integrated 30 k pull-up resistor in series with an active diode. this diode prevents the reverse current of vbus during differential voltage between vsup and bus (v bus >v sup ). t bit th rec(min) th dom(min) th rec(m a x) thre s hold s of receiving node 2 thre s hold s of receiving node 1 th dom(m a x) t s io_dom(m a x) t s io_rec(min) t s io_dom(min) t rx_pdr(2) t rx_pdf(2) t rx_pdf(1) t rx_pdr(1) t s io_rec(m a x) t bit t bit v s (tr a n s ceiver su pply of tr a n s mitting node) rx (o u tp u t of receiving node 2) rx (o u tp u t of receiving node 1) tx s io s ign a l (inp u t to tr a n s mitting node)
10 4931k?auto?06/10 ata6824 5.5 control inputs dir and pwm 5.5.1 pin dir logical input to control the direction of the external motor to be controlled by the ic. an internal pull-down resistor is included. 5.5.2 pin pwm logical input for pwm information delivered by external microcontroller. duty cycle and fre- quency at this pin are passed through to the h-br idge. an internal pull-do wn resistor is included. the internal signal on is high when ? at least one valid wd trigger has been accepted ? neither short circuit nor pbat undervoltage detected ?v bat is inside the specified range (v thuv v vbat v thov ) ? the charge pump has reached its minimum voltage ? the device temperature is not above shutdown threshold in case of a short circuit, the appropriate transistor is switched off after a blanking time of t sc . in order to avoid cross current through the bridge, a cross conduction timer is implemented. its time constant is programmable by means of an rc combination. table 5-1. status of the ic depending on control inputs and detected failures control inputs driver stage for external power mos comments on dir pwm h1 l1 h2 l2 0 x x off off off off dg1, dg2 fault or reset 1 0 pwm on off /pwm pwm motor pwm forward 1 1 pwm /pwm pwm on off motor pwm reverse table 5-2. status of the diagnostic outputs device status diagnostic outputs comments pbat_uv sc vbat_uv vbat_ov cpok ot dg1 dg2 dg3 x x x x x 1 ? ? 1 overtemperature warning x x x x 0 x 0 1 ? charge pump failure x x x 1 x x 0 1 ? overvoltage vbat x x 1 x x x 0 1 ? undervoltage vbat x 1 0 0 1 x 1 0 ? short circuit 1 x 0 0 1 x 1 0 ? undervoltage pbat note: x represents: don?t care ? no effect) pbat_uv: undervoltage pbat pin sc: short circuit drain source monitoring vbat_uv: undervoltage of vbat pin vbat_ov: overvoltage of vbat pin cpok: charge pump ok ot: overtemperature warning ? status of the diagnostic out puts depends on device status
11 4931k?auto?06/10 ata6824 5.6 vg regulator the vg regulator is used to generate the gate voltage for the low-side driver. its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. the purpose of the regulator is to limit the gate voltage for the external power mos transistors to 12v. it needs a ceramic capacitor of 470 nf for stability. the output voltage is reduced if the supply vo ltage at vbat falls below 12v. 5.7 charge pump the integrated charge pump is needed to supply the gates of the external power mos transis- tors. it needs a shuffle capacitor of 220 nf and a reservoir capacitor of 470 nf. without load, the output voltage on the reservoir capacitor is v vbat plus vg. the charge pump is clocked with a dedicated internal oscillator of 100 khz. the charge pump is designed to reach a good emc level. the charge pump will be switched off for v vbat > v thov . 5.8 thermal shutdown there is a thermal shutdown block implemented. wi th rising junction temperature, a first warning level will be reached at 180c. at this point th e ic stays fully function al and a warning will be sent to the microcontroller. at junction temperature 200c the drivers for h1, h2, l1, l2, sio and the vcc regulator will be s witched off and a reset occurs. 5.9 h-bridge driver the ic includes two push-pull drivers for control of two external power nm os used as high-side drivers and two push-pull drivers for control of two external power nmos used as low-side driv- ers. the drivers are able to be used with standard and logic-level power nmos. the drivers for the high-side control use the charge pump voltage to supply the gates with a volt- age of vg above the battery voltage level. the low-side drivers are supplied by vg directly. it is possible to control the external load (motor) in the forward and reverse direction (see table 5-1 on page 10 ). the duty cycle of the pmw controls the speed. a duty cycle of 100% is possible in both directions. 5.9.1 cross conduction time to prevent high peak currents in the h-bridge, a non-overlapping phase for switching the exter- nal power nmos is realized. an external rc combination defines the cross conduction time in the following way: t cc (s) = 0.41 r cc (k ) c cc (nf) (tolerance: 5% 0.15 s) the rc combination is charged to 5v and the switching level of the internal comparator is 67% of the start level. the resistor r cc must be greater than 5 k and should be as close as possible to 10 k , the c cc value has to be 5 nf. use of cog capacitor material is recommended. the time measurement is triggered by the pwm or dir signal crossing the 50% level.
12 4931k?auto?06/10 ata6824 figure 5-6. timing of the drivers the delays t hxlh and t lxlh include the cross conduction time t cc . 5.10 short circuit detection to detect a short in h-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power nmos. if the transistors are switched on and the source-drain voltage difference is higher than the value v sc (4v with tolerances) the diagno- sis pin dg1 will be set to ?h? and the drivers will be switched off. all gate driver outputs (hx and lx) will be set to ?l?. releasing the gate driver outputs will set dg1 ba ck to ?l?. with the next tran- sition on the pin pwm, the corr esponding drivers, depending on the dir pin, will be switched on again. there is a pbat supervision block implemented to detect the possible voltage drop on pbat during a short circuit. if the voltage at pbat falls under v pbat_ok the drivers will be switched off and dg1 will be set to ?h?. it will be cleared as soon as the pbat undervol tage condition disappears. the detection of drain source voltage exceedances is activated after the short circuit blanking time t sc , the short circuit detection of pbat failures operates immediately. t lxlh t lxr t hxlh t hxr t cc t hxhl t hxf t lxhl t lxf t cc hx lx pwm or dir 80% 50% 20% 80% 20% t t t
13 4931k?auto?06/10 ata6824 6. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . pin description pin name min max unit ground gnd 0 0 v power ground pgnd ?0.3 +0.3 v reverse protected battery voltage vbat +40 v reverse current out of pin vbat ?1 ma reverse protected battery voltage pbat +40 v reverse current out of pin pbat ?500 ma digital output /reset ?0.3 v vcc + 0.3 v digital output dg1, dg2, dg3 ?0.3 v vcc + 0.3 v 4.9v output, external blocking capacitor vint ?0.3 +5.5 v cross conduction time capacitor/resistor combination cc ?0.3 v vcc + 0.3 v digital input coming from microcontroller wd ?0.3 v vcc + 0.3 v watchdog timing resistor rwd ?0.3 v vcc + 0.3 v digital input direction control dir ?0.3 v vcc + 0.3 v digital input pwm control + test mode pwm ?0.3 v vcc + 0.3 v 5v regulator output vcc ?0.3 +5.5 v digital input vmode ?0.3 v vint + 0.3 v 12v output, external blocking capacitor vg ?0.3 +16 v digital output rx ?0.3 v vcc + 0.3 v digital input tx ?0.3 v vcc + 0.3 v serial interface data pin sio ?27 (1) v vbat + 2 v source external high-side nmos s1, s2 ?2 +30 +40 (4) v gates external low-side nmos l1, l2 v pgnd ? 0.3 v vg + 0.3 v gates of external high-side nmos h1, h2 v sx ? 1 (3) v sx + 16 (3) v charge pump cplo ?0.3 v pbat + 0.3 v charge pump cphi ?0.3 v vres + 0.3 v charge pump output vres ?0.3 +40 (5) v switched vbat vbatsw ?0.3 v vbat + 0.3 v power dissipation p tot 1.4 (2) w storage temperature ? store ?55 +150 c notes: 1. for v vbat 13.5v 2. may be additionally limited by external thermal resistance 3. x = 1.2 4. t < 0.5s 5. load dump of t < 0.5s tolerated
14 4931k?auto?06/10 ata6824 7. thermal resistance parameters symbol value unit thermal resistance junc tion to heat slug r thjc <5 k/w thermal resistance junction to ambient when heat slug is soldered to pcb r thja 25 k/w 8. operating range the operating conditions define the limits for functional operat ion and parametric characteristics of the device. functionality outside these limits is not implied unless otherwise stated explicitly. parameters symbol min max unit operating supply voltage (1) v vbat1 v thuv v thov v operating supply voltage (2) v vbat2 6< v thuv v operating supply voltage (3) v vbat3 4.5 < 6 v operating supply voltage (4) v vbat4 0< 4.5v operating supply voltage (5) v vbat5 > v thov 40 v junction temperature range under bias t j ?40 +200 c normal functionality t a ?40 +150 c normal functionality, overtemperature warning set t j 165 195 c switch-off temperatures of drivers for h1, h2, l1, l2, sio and of vcc regulator t j 185 215 c note: 1. full functionality 2. h-bridge drivers are switched off (undervoltage detection) 3. h-bridge drivers are switched off, 5v/3.3v regu lator with reduced parameters, reset works correctly 4. h-bridge drivers are switched off, 5v regulator not working, reset not correct 5. h-bridge drivers are switched off 9. noise and surge immunity parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression iec-cispr25 level 5 esd (human body model) esd s 5.1 2 kv (2) cdm (charge device model) esd stm5.3. 500v notes: 1. test pulse 5: v vbmax = 40v 2. exception: 1 kv at pin 8 (sio)
15 4931k?auto?06/10 ata6824 10. electrical characteristics all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* 1 power supply and supervisor functions 1.1 current consumption v vbat v vbat = 13.5v (1) 25, 30 i vbat1 7maa 1.2 internal power supply 2 v int 4.84.945.1 va 1.3 band gap voltage 3 v bg 1.235 v a 1.4 overvoltage threshold up v vbat 30 v thov_up 21.2 22.7 v a 1.4.1 overvoltage threshold down v vbat 30 v thov_down 19.8 21.3 v a 1.5 overvoltage threshold hysteresis v vbat 30 v tovhys 12.4va 1.6 undervoltage threshold up v vbat 30 v thuv_up 6.8 7.4 v a 1.6.1 undervoltage threshold down v vbat 30 v thuv_down 6.5 7.0 v a 1.7 undervoltage threshold hysteresis v vbat measured during qualification only 30 v tuvhys 0.2 0.6 v a 1.8 on resistance of v vbat switch v vbat = 13.5v 31 r on_vbatsw 100 a 1.9 undervoltage threshold pbat v vbat = 13.5v 25 v pbat_ok 6.1 7 v a 1.10 undervoltage threshold hysteresis pbat v vbat = 13.5v 25 v pbat_ok_hyst 0100mva 2 5v/3.3v regulator 2.1 regulated output voltage 9v < v vbat < 40v, i load = 0 ma to 100 ma 29 v cc1 4.85 (3.2) 5.15 (3.4) v a 2.2 regulated output voltage 6v < v vbat 9v i load = 0 ma to 100 ma 29 v cc2 4.75 (3.2) 5.25 (3.4) v a 2.2a regulated output voltage 6v < v vbat 9v i load = 0 ma to 80 ma t a > 125c 29 v cc2 4.75 (3.2) 5.25 (3.4) v a 2.3 line regulation i load = 0 ma to 100 ma 29 dc line regulation <1 50 mv a 2.4 load regulation i load = 0 ma to 100 ma 29 dc load regulation <10 50 mv a 2.5 output current limitation v vbat > 6v 29 i os1 100 350 ma a * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section ?cross conduction time? 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 5-5 on page 9 ?definition of bus timing parameters?
16 4931k?auto?06/10 ata6824 2.6 serial inductance to c vcc including pcb 29 esl 1 20 nh d 2.7 serial resistance to c vcc including pcb 29 esr 0 0.5 d 2.8 blocking cap at vcc (2), (3) 29 c vcc 1.1 3.3 f d 2.9 high threshold vmode 1 vmode h 4.0 v a 2.10 low threshold vmode 1 vmode l 0.7 v a 3vg regulator 3.1 regulated output voltage v pbat 14v i max = 20 ma 24 v vg 11 14 v a 3.2 regulated output voltage v pbat = 9v i max = 20 ma 24 v vg 7.0 9.0 v a 4 reset and watchdog 4.1 v cc threshold voltage level for /reset vmode = ?h? (vmode = ?l?) 29 v thresh 4.9 (3.25) v a 4.1a tracking of reset thres-hold with regulated output voltage vmode = ?h? (vmode = ?l?) 29 v vcc1-vthresh 75 (50) mv a 4.2 v cc threshold voltage level for /reset vmode = ?h? (vmode = ?l?) 29 v thresl 4.3 (2.86) v a 4.3 hysteresis of /reset level vmode = ?h? (vmode = ?l?) (4) 29 hys resth 70 200 350 (240) mv a 4.4 length of pulse at /reset pin (5) 5t res 7000 t 100 a 4.5 length of short pulse at /reset pin (5) 5t resshort 200 t 100 a 4.6 wait for the first wd trigger (5) 5t d 7000 t 100 a 4.7 time for vcc < v thresl before activating /reset (4) 29 t delayresl 0.5 2 s c 4.8 resistor defining internal bias currents for watchdog oscillator 3r rwd 10 91 k d 4.9 watchdog oscillator period r rwd = 33 k 3t osc 11.09 13.55 s a 4.11 watchdog input low-voltage threshold 6v ilwd 0.3 v vcc va 10. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section ?cross conduction time? 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 5-5 on page 9 ?definition of bus timing parameters?
17 4931k?auto?06/10 ata6824 4.12 watchdog input high-voltage threshold 6v ihwd 0.7 v vcc va 4.13 hysteresis of watchdog input voltage threshold 6v hyswd 0.3 0.8 v a 4.14 close window (5) 6t1 980 t osc a 4.15 open window (5) 6t2 780 t osc a 4.16 output low-voltage of /reset at i olres = 1 ma 5 v olres 0.4 v a 4.17 internal pull-up resistor at pin /reset 5r pures 5 10 15 k a 5 high voltage serial interface 5.1 low-level output current normal mode; v sio =0v, v rx =0.4v 13 il rx 2maa 5.2 high-level output current normal mode; v sio =v vbat v rx =v cc ?0.4v 13 ih rx 0.8 ma a 5.4 driver dominant voltage v busdom_drv_losup v vbat = 7.3v r load = 500 8v _losup 1.2 v a 5.5 driver dominant voltage v busdom_drv_hisup v vbat = 18v r load = 500 8v _hisup 2va 5.6 driver dominant voltage v busdom_drv_losup v vbat = 7.3v r load = 1000 8v _losup_1k 0.6 v a 5.7 driver dominant voltage v busdom_drv_hisup v vbat = 18v r load = 1000 8v _hisup_1k_ 0.8 v a 5.8 pull up resistor to vbat the serial diode is mandatory 8r sio 20 30 60 k a 5.9 current limitation v sio = v bat_max 8i sio_lim 40 250 ma a 5.9a current limitation in case of reset and sio overheat v sio = v bat_max reset = high 8i sio_lim_reset 30 100 ma a 5.10 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v sio = 0v v vbat = 12v 8i sio_pas_dom ?1 ma a 10. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section ?cross conduction time? 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 5-5 on page 9 ?definition of bus timing parameters?
18 4931k?auto?06/10 ata6824 5.11 leakage current sio recessive driver off 8v < v vbat < 18v 8v < v sio < 18v v sio v vbat 8i sio_pas_rec 30 a a 5.12 leakage current at ground loss control unit disconnected from ground loss of local ground must not affect communication in the residual network gnd device = vs v vbat =12v 0v < v sio < 18v 8i sio_no_gnd ?1 1 ma a 5.13 node has to sustain the current that can flow under this condition. bus must remain operational under this condition v vbat disconnected v sup_device = gnd 0v < v sio < 18v 8i sio 100 a a 5.14 center of receiver threshold v sio_cnt = (v th_dom +v th_rec )/2 8v sio_cnt 0.475 vs 0.5 vs 0.525 vs v a 5.15 receiver dominant state v en = 5v 8 v siodom 0.4 vs v a 5.16 receiver recessive state v en = 5v 8 v siorec 0.6 vs v a 5.17 receiver input hysteresis v hys = v th_rec ? v th_dom 8v siohys 0.1 vs 0.175 vs v a 5.18 duty cycle 1 th rec(max) = 0.744 v vbat th dom(max) = 0.581 v vbat v vbat = 7v to 18v t bit = 50 s d1 = t sio_rec(min) / 2 t bit (11) 8d10.380 a 5.19 duty cycle 2 th rec(min) = 0.422 v vbat th dom(min) = 0.284 v vbat v vbat = 7v to 18v t bit = 50 s d2 = t sio_rec(max) / 2 t bit (11) 8 d2 0.600 a 5.20 propagation delay of receiver t rec_pd = max(t rx_pdr ,t rx_pdf ) (11) 7v < v vbat < 18v 8t rx_pd 6sa 5.21 symmetry of receiver propagation delay t rx_sym = t rx_pdr ? t rx_pdf (11) 7v < v vbat < 18v 8t rx_sym ?2 +2 s a 10. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section ?cross conduction time? 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 5-5 on page 9 ?definition of bus timing parameters?
19 4931k?auto?06/10 ata6824 6 control inputs dir, pwm, wd, tx 6.1 input low-voltage threshold 10, 11, 6, 9 v il 0.3 v vcc va 6.2 input high-voltage threshold 10, 11, 6, 9 v ih 0.7 v vcc va 6.3 hysteresis 10, 11, 6, 9 hys 0.3 0.5 0.8 v a 6.4 pull-down resist or dir, pwm, wd, tx 10, 11, 6, 9 r pd 25 50 140 k a 6.5 rise/fall time 10, 11, 6, 9 t rf 100 ns a 7charge pump 7.1 charge pump voltage load = 0a 21 vcp v vbat + v vg va 7.2 charge pump voltage load = 3 ma, c cp = 100 nf 21 vcp v vbat + v vg ? 1 va 7.3 period charge pump oscillator 21 t 100 911sa 7.4 cp load current in vg without cp load load = 0a 21 i vgcpz 600 a a 7.5 cp load current in vg with cp load load = 3 ma, c cp = 100 nf 21 i vgcp 4maa 7.6 charge pump ok threshold up reference: pbat 21 v cpok_up 5.3 6.3 v a 7.7 charge pump ok threshold down reference: pbat 21 v cpok_down 4.5 5.5 v a 7.8 charge pump ok hysteresis 21 v cpok_hys 0.3 1.3 v a 8 h-bridge driver 8.1 low-side driver high output voltage 26, 27 v lxh v vg ? 0.5v v vg va 8.2 on-resistance of sink stage of pins l1, l2 26, 27 r dson_lxl, x = 1, 2 25 a 8.3 on-resistance of source stage of pins l1, l2 26, 27 r dson_lxh, x = 1, 2 25 a 10. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section ?cross conduction time? 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 5-5 on page 9 ?definition of bus timing parameters?
20 4931k?auto?06/10 ata6824 8.4 output peak current at pins l1, l2, switched to low v lx = 3v 26, 27 i lxl, x = 1, 2 100 ma a 8.5 output peak current at pins l1, l2, switched to high v lx = 3v 26, 27 i lxh, x = 1, 2 ?100 ma a 8.6 pull-down resistance at pins l1, l2 26, 27 r pdlx x = 1, 2 25 140 k a 8.7 on-resistance of sink stage of pins h1, h2 v sx = 0 18, 20 r dson_hxl, x = 1, 2 25 a 8.8 on-resistance of source stage of pins h1, h2 v sx = v vbat 18, 20 r dson_hxh, x = 1, 2 25 a 8.9 output peak current at pins hx, switched to low v vbat = 13.5v v sx = v vbat v hx = v vbat + 3v 18, 20 i hxl, x = 1, 2 100 ma a 8.10 output peak current at pins hx, switched to high v vbat = 13.5v v sx = v vbat v hx = v vbat + 3v 18, 20 i hxh, x = 1, 2 ?100 ma a 8.11 static switch output low voltage at pins hx and lx v sx = 0v i hx = 1 ma, i lx = 1 ma 18, 20, 26, 27 v hxl , v lxl x = 1, 2 0.3 v a 8.12 static high-side switch output high-voltage pins h1, h2 i lx = ?10 a (pwm = static) 18, 20 v hxhstat1 (7) v vbat + v vg ? 1 v vbat + v vg va 8.13 sink resistance between hx and sx switches off 17, 18, 19, 20 r pdhx 25 140 k a dynamic parameters 8.15 propagation delay time, low-side driver from high to low figure 5-6 on page 12 v vbat = 13.5v 26, 27 t lxhl 0.5 s a 8.16 propagation delay time, low-side driver from low to high v vbat = 13.5v 26, 27 t lxlh 0.5 + t cc s a 8.17 fall time low-side driver v vbat = 13.5v c gx =5 nf 26, 27 t lxf 0.5 s a 8.18 rise time low-side driver v vbat = 13.5v 26, 27 t lxr 0.5 s a 8.19 propagation delay time, high-side driver from high to low figure 5-6 on page 12 v vbat = 13.5v 18, 20 t hxhl 0.5 s a 10. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section ?cross conduction time? 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 5-5 on page 9 ?definition of bus timing parameters?
21 4931k?auto?06/10 ata6824 8.20 propagation delay time, high-side driver from low to high v vbat = 13.5v 18, 20 t hxlh 0.5 + t cc s a 8.21 fall time high-side driver v vbat = 13.5v, c gx = 5 nf 18, 20 t hxf 0.5 s a 8.22 rise time high-side driver v vbat = 13.5v 18, 20 t hxr 0.5 s a 8.24 external resistor 4 r cc 5k d 8.25 external capacitor 4 c cc 5nfd 8.26 r on of t cc switching transistor 4r oncc 200 a 8.27 cross conduction time (8) r cc = 10 k c cc = 1 nf 4t cc 3.75 4.45 s a 8.28 short circuit detection voltage (9) 17, 19 v sc 3.544.7va 8.29 short circuit blanking time (10) 17, 19 t sc 51015sa 9 diagnostic outputs dg1, dg2, dg3 9.1 low level output current v dg = 0.4v (6) 14, 15, 16 il 2 ma a 9.2 high level output current v dg = vcc ? 0.4v (6) 14, 15, 16 ih 0.8 ma a 10. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 150c unless stated otherwise. no. parameters test conditions pin symbol min typ max unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t 100 ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section ?cross conduction time? 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc 11. see figure 5-5 on page 9 ?definition of bus timing parameters?
22 4931k?auto?06/10 ata6824 11. errata 11.1 faulty pulse at dg1 a faulty pulse of approximately 100 ns appears at pin 16 (dg1) ? signalizing short circuit condi- tion ? under following circumstances: general condition: pwm = high and detected undervo ltage of vbat (signalized at pin 15 = dg2) or detected overvoltage of vbat (signalized at pin 15 = dg2) or detected undervoltage of the charge pump (signalized at pin 15 = dg2) or overtemperature shutdown 11.2 problem fix/workaround set software to ignore the faulty pulse.
23 4931k?auto?06/10 ata6824 13. package information 12. ordering information extended type number package remarks ata6824-pnqw qfn32, 5 mm 5 mm pb-free ata6824-mfhw tpqfp32, 7 mm 7 mm pb-free 0.9 0.1 0.23 0.07 0.4 0.1 3.6 0.15 0.2 z 10:1 z 3.5 0.5 nom. 32 16 9 25 32 top bottom pin1 identification 24 17 1 8 1 5 17 specifications according to din technical drawings issue: 1; 28.11.05 drawing-no.: 6.543-5124.01-4 not indicated tolerances 0.05 dimensions in mm package: qfn_ 5 x 5_32l exposed pad 3.6 x 3.6
24 4931k?auto?06/10 ata6824 title drawing no. rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 6.54 3 -5157.01-4 common dimen s ion s (unit of me asu re = mm) min nom note max s ymbol 1 ( a cc. jedec outline) packa g e: epad tpqfp 3 2 11/25/0 8 a2 dimen s ion s in mm s pecific a tion s a ccording to din technic a l dr a wing s 0.15 0.05 a1 3 .5 b s c d2 3 .5 b s c e2 0. 3 0.45 0. 3 7 b 0.45 0.75 0.6 l 0. 8 b s c e 3 2 n 7 b s c e1 9 b s c e 7 b s c d1 9 b s c d 1 1.05 0.95 a2 1.2 a d d1 9 1 3 2 16 l e2 b 3 2 17 24 8 1 25 e1 e a d2 a1 e
25 4931k?auto?06/10 ata6824 14. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4931k-auto-06/10 ? package drawing tpqfp32 on page 24 changed 4931j-auto-02/10 ? section 5.1.3 ?temperature supervisor? on page 6 changed ? section 5.4 ?high voltage serial interface? on page 9 changed ? section 5.5.2 ?pin pwm? on page 10 changed ? section 5.8 ?thermal shutdown? on page 11 changed ? section 5.10 ?short circuit detection? on page 12 changed ? section 6 ?absolute maximum ratings? on page 13 changed ? section 8 ?operating range? on page 14 changed ? section 10 ?electrical characteristics? number 8.29 on page 21 changed 4931i-auto-12/09 ? section 5.1.3 ?temperature supervisor? on page 6 changed ? section 5.3.1 ?timing sequence? on page 8 changed ? section 5.4 ?high voltage serial interface? on page 9 changed ? section 5.5.2 ?pin pwm? on page 10 changed ? section 5.10 ?short circuit detection? on page 12 changed ? section 10 ?electrical characteristics? numbers 4.4 and 4.6 on page 16 changed ? section 10 ?electrical characteristics? number 5.9a on page 17 added ? section 10 ?electrical characteristics? numbers 7.6 and 7.7 on page 19 changed ? section 10 ?electrical characteristics? number 7.8 on page 19 added 4931h-auto-11/09 ? section 5.10 ?short circuit detection? on page 12 changed ? section 10 ?electrical characterist ics? numbers 1.9 and 1.10 on page 15 added 4931g-auto-04/09 ? section 9 ?noise and surge immunity? on page 14 changed 4931f-auto-02/09 ? v vat to v vbat in whole document changed ? v bat to v vbat in whole document changed ? features on page 1 changed ? section 1 ?description? on page 1 changed ? table 4-1 ?typical external components (see also figure 1-1 on page 2)? on page 5 changed ? figure 5-1 ?voltage dependence and timing of vcc controlled reset? on page 7 added ? figure 5-5 ?definition of bus timing parameters? on page 9 changed ? section 5.7 ?charge pump? on page 11 changed ? section 6 ?absolute maximum ratings? on page 13 changed ? section 8 ?operating range? on page 14 changed ? section 10 ?electrical characteristics? on pages 15 to 21 changed ? section 11 ?errata? on page 21 added ? section 12 ?ordering information? on page 22 changed ? section 13 ?package information? on page 22 changed 4931e-auto-01/08 ? section 5.2 ?5v/3.3v vcc regulator? on pages 6 to 7 changed ? section 5.4 ?high voltage serial interface? on page 9 changed ? section 10 ?electrical characterist ics? numbers 4.1a and 4.3 on page 16 changed
4931k?auto?06/10 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en-yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support auto_control@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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